`include "inc.vh"

module tb_top;

   logic rst = 1;
   logic clk = 0;
   logic [7:0] count;


   initial forever #5 clk = ~clk;
   
   initial begin
	  #20 rst = 0;
   end

   counter U_counter(
					 .rst(rst),
					 .clk(clk),
					 .count(count) );
endmodule // tb

   